A metal oxide semiconductor field effect transistor (MOSFET) is used in forming dynamic random access memory (DRAM) cells. A DRAM circuit typically includes an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to, memory cells are achieved by activating selective wordlines and bitlines. Typically, a DRAM cell comprises a MOSFET connected to a capacitor. The capacitor includes two electrodes that are separated by a node dielectric, while the MOSFET includes a gate and diffusion regions that are referred to as either the source or drain region, depending on the operation of the transistor.
There are different types of MOSFETs known to those skilled in the art. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Trench capacitors are frequently employed with DRAM cells. A trench capacitor is a three-dimensional structure formed into a semiconductor substrate. The structure is normally formed by etching trenches having a high aspect ratio (a depth to width ratio of greater than 3.0) into the substrate. Trench capacitors commonly have N+ doped polysilicon or another conductive material as one electrode of the capacitor (i.e., the storage node) and the other electrode of the trench capacitor is a buried plate that is formed via outdiffusion of dopants, typically arsenic, into a portion of the substrate surrounding the lower portion of the trench.
The functionality of DRAM arrays that use deep trench storage nodes requires the electrical isolation of the plate side of the capacitor and the transfer device. This is accomplished using a parasitic npn transistor structure along the trench sidewall. Due to process variability during the formation of the outdiffused buried plate, arsenic residuals can contaminate the sidewalls of the deep trench.
The arsenic residuals, in turn, counter dope the array well disposed in the substrate after the drive-in anneal, and result in leakage of the plate charge to the transfer field effect transistor (FET) due to a lower threshold voltage of the parasitic device. This problem will cause fails in the writeback and signal margin tests of the cell and thereby reduce functionality and yield.
A typical prior art process of fabricating a portion of a trench capacitor structure is shown, for example, in FIGS. 1A-1H. Specifically, FIG. 1A shows an initial structure 10 that includes a semiconductor substrate 12 having at least one deep trench opening 14 located therein. The at least one deep trench opening 14 is formed by conventional lithography and etching. After etching and stripping of the photoresist mask, an arsenic doped silicate glass (ASG) layer 16 is conformally deposited on the horizontal surfaces of the substrate 12 and on exposed wall portions of the at least one deep trench opening 14.
Next, and as shown in FIG. 1B, a photoresist 18 is then deposited on the initial structure 10 shown in FIG. 1A. As is depicted in FIG. 1B, the photoresist 18 is located on the ASG layer 16. The resist layer 18 fills the at least one deep trench opening 14 and extends on the horizontal surface of the ASG layer 16 that is disposed above the upper surface of the substrate 12.
FIG. 1C shows the structure that is formed after the photoresist 18 is recessed into a lower portion of the at least one deep trench opening 14 utilizing an etching process that is selective to the photoresist material. Next, an etching process is performed to recess the ASG layer 16. Under ideal circumstances, this etching process is intended to completely remove the ASG layer 16 within the at least one deep trench opening 14 that is not protected by the recessed photoresist 18. However, as shown in FIG. 1D, this step within the prior art process leaves residual ASG 16′ on the exposed sidewalls of the substrate 12 within the at least one deep trench opening 14. The residual ASG layer 16′ is typically tapered outward from the upper surface of the substrate 12 at the mouth of the at least one deep trench opening 14 and extending down the sidewalls of the at least one trench opening 14. As such, the residual ASG layer 16′ becomes thicker as its depth within the at least one deep trench opening 14 increases.
Next, a dielectric cap 20 such as an oxide is formed providing the structure that is illustrated in FIG. 1E. As shown, the dielectric cap 20 is located within the at least one deep trench opening 14 and atop the horizontal surface of the substrate 12 that extends from the mouth of the at least one deep trench opening 14. An annealing step which drives-in As is then performed providing the structure shown in FIG. 1F. As illustrated, the anneal step forms the n-type buried plate 22 along an exterior bottom portion of the at least one deep trench opening 14. Additionally, and due to the presence of the residual ASG layer 16′ remaining within the at least one deep trench opening 14, an As doped region 24 is formed within the substrate 12 along the exterior sidewalls of the at least one deep trench opening 14. As shown, this As doped region 24 is in contact with the buried plate 22 and it extends vertically to the surface of the substrate 12.
FIG. 1G illustrates the structure of FIG. 1F after removing the dielectric cap 20 and stripping of the ASG layer 16 including the residual ASG layer 16′ from within the at least one deep trench opening 14. As shown, a portion of a p-well 13 along the exterior sidewalls of the at least one deep trench opening 14 is counter doped by the As doped region 24. FIG. 1H shows the structure of FIG. 1G after formation of a collar 26 and n-type diffusion regions 28.
As stated above, the presence of the arsenic residuals counter dopes the array well after the drive-in anneal, and results in leakage of the plate charge to the transfer field effect transistor (FET) due to a lower threshold voltage of the parasitic device. This problem will cause fails in the writeback and signal margin tests of the cell and thereby reduce functionality and yield.
In view of the arsenic contamination problem mentioned in prior art trench capacitor structures, there is a need for providing a trench capacitor structure in which such arsenic contamination is substantially reduced or essentially eliminated.